1. Field of the Invention
The present invention relates to a manufacturing method for a semiconductor device, to a semiconductor device made thereby, and to an electronic apparatus provided with the semiconductor device.
Priority is claimed to Japanese Patent Application No. 2003-82965, filed May 25, 2003, which is incorporated herein by reference.
2. Description of Related Art
Presently, due to the implementation of downsizing and weight reduction in portable electronic apparatuss such as notebook computers, PDAs (Personal Data Assistants) and the like, and devices such as sensors, micromachines, and heads for printers, research and development related to downsizing various types of electronic components such as the semiconductor chips provided therein is flourishing. In addition, in order to increase the added value, increasingly high functionality of these electronic apparatuss is being planed, and increasingly high functionality and high speed are also required for the electronic components provided within these electronic apparatuss.
System LSI (Large Scale Integration) is one example of an electronic component that has a high functionality, but time is required to commercialize system LSI. In the current situation, system LSI has failed to maintain the recent development cycle of electronic apparatuss. Thus, SIP (System in Package) technology has been proposed. In SIP, various functions among the plurality of functions contained in system LSI are provided on one IC (Integrated Circuit), and these chips are combined to realize a system LSI in one package.
In SIP technology, this is implemented by stacking a plurality of ICs three-dimensionally, but in order for the stacked ICs to function as system LSI, each must be electrically connected to the other. Conventionally, the electrodes formed on each IC are electrically connected by using a wire bonding technology, but in connections by wire bonding, the wiring length becomes long, and thus there is a limit to downsizing the packaging.
Thus, a three-dimensional packaging technology has been proposed wherein ICs are thinned by carrying out an etching process or a grinding process on the bottom surface of the IC, and at the same time connecting terminals consisting of metals are formed that pass through the upper surface and the bottom surface of the IC, and the connecting portions formed on the stacked ICs are bonded, thereby providing electrical connection between the ICs. Refer, for example, to Japanese Patent Application Laid-Open (JP-A) No. 2001-44197 for details of this three-dimensional packaging technology.
The electrical components manufactured by stacking chips using the three-dimensional packaging technology described above are sealed in a sealing resin, and thus it is possible to guarantee a certain degree of reliability. However, in the case that the electrical component is mounted in a portable electrical device, it is necessary to guarantee a higher strength because it can be anticipated that strong vibrations and shocks will be received from the outside.
In order to implement a further increase in the reliability of the electrical components, it is necessary to increase the bonding strength between the connecting terminals formed on each of the ICs. In the conventional electrical component fabricated using three-dimensional packaging technology, the distal ends (the part that bonds with the other chip) of the connecting terminals formed on the IC usually have a flat shape. Thus, the bonding between the connecting terminals of the stacked chips is two-dimensional, and there is the problem that the bonding strength is low, and thereby the reliability is low.
In consideration of the problem described above, it is an object of the present invention to provide a manufacturing method for a semiconductor device and a semiconductor device that can increase the bonding strength of the stacked semiconductor chips and thereby guarantee a high reliability, and an electronic apparatus equipped with this semiconductor device.